Stream: Virtual Room 3
Time: 15:00 - 15:45
The speaker, an STSM in IBM Z Performance and Microprocessor Development, will discuss v5 (newly updated for z17) of The IBM Z Processor Optimization Primer document now available online. The platform's processor subsystems are described with focus on the core microarchitectures from z196 to z17. High level insights with information and potential methods to optimize for code performance will also be provided. Put on your propeller hat and come join us for a truly fascinating session!
20+ years experience in system performance and computer hardware development, primarily with IBM Z's Microprocessor family. Client-facing lab representative for HW system performance inquiries and situations worldwide. Large Systems Performance Reference (LSPR) capacity rating development. Outstanding Technical Achievement Award received for developing IBM's standard core performance modeling environment. Led and coded alongside the processor modeling team that developed five generations of IBM Z core performance models and delivered several hundred studies per generation along with ideas that shaped the hardware designs and supplied projection data to brand/marketing. Developed a verification environment and several modules stressing cache and address-translation macro designs. Developed fixed point unit and instruction fetch unit logic/VHDL macros and multiplier dataflow. Project managed team of 20+ and verification co-lead for Agere switch-fabric chipset design. IBM Master Inventor and co-author of ~30 patents.
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