20+ years experience in system performance and computer hardware development, primarily with IBM Z's Microprocessor family. Client-facing lab representative for HW system performance inquiries and situations worldwide. Large Systems Performance Reference (LSPR) capacity rating development. Outstanding Technical Achievement Award received for developing IBM's standard core performance modeling environment. Led and coded alongside the processor modeling team that developed five generations of IBM Z core performance models and delivered several hundred studies per generation along with ideas that shaped the hardware designs and supplied projection data to brand/marketing. Developed a verification environment and several modules stressing cache and address-translation macro designs. Developed fixed point unit and instruction fetch unit logic/VHDL macros and multiplier dataflow. Project managed team of 20+ and verification co-lead for Agere switch-fabric chipset design. IBM Master Inventor and co-author of ~30 patents.
Email: hutton@us.ibm.com
Linked In: https://www.linkedin.com/in/david-hutton-a9ab2a1/